1. Field of the Invention
The present invention relates to an internal-clock adjusting circuit to adjust a timing of an internal clock signal.
2. Description of Related Art
Data is input to or output from a semiconductor device such as an SDRAM (Synchronous Dynamic Random Access Memory) synchronously with a clock signal supplied from outside (hereinafter, “external clock signal”). However, when the semiconductor device outputs data while using the external clock signal as a timing signal, a phase of the output data slightly lags behind that of the external clock signal because of an operating delay in an output buffer circuit. To avoid this delay, the semiconductor device often generates an internal clock signal having a phase advanced by an internal-clock adjusting circuit such as a DLL (Delay Locked Loop) circuit by as much as the operating delay, and outputs data while using the internal clock signal as a timing signal.
The internal-clock adjusting circuit adjusts a phase of the internal clock signal in a direction of decreasing a phase difference between the external clock signal and the internal clock signal at regular intervals, for example, at intervals of 16 clocks after power-on. Specifically, the internal-clock adjusting circuit decreases the phase difference by adjusting a timing of a rising edge of the internal clock signal. When the phase difference is within a minimum resolving power of the internal-clock adjusting circuit, then the DLL circuit turns into a DLL locked state and the internal clock signal follows the external clock signal. Thereafter, the internal-clock adjusting circuit readjusts the phase of the internal clock signal when another phase difference occurs.
Furthermore, a duty cycle of the internal clock signal is desirably about 50%. Therefore, the internal-clock adjusting circuit adjusts the duty cycle of the internal clock signal to be closer to 50% at intervals of, for example, 32 clocks. Specifically, the internal-clock adjusting circuit makes the duty cycle of the internal clock signal closer to the ideal value of 50% by adjusting a timing of a falling edge of the internal clock signal. When a deviation of the duty cycle is eliminated, the DLL circuit turns into a DLL locked state. Thereafter, the internal-clock adjusting circuit readjusts the duty cycle of the internal clock signal when another duty cycle deviation occurs. A conventional DLL circuit is disclosed in Japanese Patent Application Laid-Open Nos. 2003-110411 and 2008-060842.
When an adjustment amount per adjustment is set small, the internal-clock adjusting circuit can make a fine adjustment. However, when a timing of an edge largely deviates from a target timing in an unlocked state, it takes long time to reach the locked state. At the time of power-on, in particular, the deviation tends to be large. When the adjustment amount per adjustment is set large, time reduction can be achieved. However, because of coarse adjustment, the timing of the edge tends to deviate from the target timing in the locked state.